1. Field of the Invention
This invention relates to the field of driver circuits for generating non-overlapping clock output signals.
2. Background Art
In an integrated circuit device, it is often desired to utilize a plurality of clocking signals for various portions of the circuit. In order to maximize efficiency, it is preferred to generate all clocking signals used on the integrated circuit from a single clock input. In the prior art, this was accomplished by coupling a clock input signal to a divider circuit, which had one or more output signals of varying frequencies. In order to effectively use these multiple clocking signals, it is necessary to drive them so that they are non-overlapping. In the past, this was accomplished by using cross-coupled or gates. A disadvantage of this prior art method is the susceptibility of such gates to process variations. Additionally, when the clocking signals included phases which were complements of other phases, a large amount of skew was introduced between the true signal and the complement of that signal.
Therefore, it is an object of the present invention to provide a driver circuit which results in the output of non-overlapping clocking signals.
It is further an object of the present invention to provide a driver circuit which is process insensitive.
It is yet another object of the present invention to provide a clock driver circuit which results in a minimum of skew between a true signal and its complement.
It is still a further object of the present invention to provide a clock driver circuit which results in improved and efficient operation.